High power solid-state devices able to amplify radio frequency (“RF”) and microwave signals are used today in a variety of applications, for example in cell phones and other wireless communication systems. Bipolar junction transistors, including heterojunction bipolar transistors (HBTs), are commonly used in such systems for amplifying small-amplitude signals and delivering amplified RF power to an antenna. Although bipolar junction transistors (BJTs) are used herein to describe the background of this invention, this is by way of example and does not limit the scope of the invention disclosed herein.
High power solid-state devices for amplifying RF and microwave signals can be fabricated using a variety of materials, but silicon germanium (“SiGe”) and gallium arsenide (“GaAs”) are the most widely used materials for commercial applications at the present time. Most power amplifiers for cell phones are made using GaAs, because current fabrication technologies using that material can deliver devices with relatively high power output (1-4 W) at the relatively low frequencies (800 Mhz-1.9 Ghz) used by most cell phones. Most power amplifiers for wireless networking products use SiGe, because current fabrication technologies using that material can allow high level integration to reduce cost deliver devices that can operate at somewhat higher frequencies (2.4 Ghz-60 Ghz) but at the reduced power (10-200 mW typical) used by wireless networking products such as 802.11b (“WiFi”). Besides the electronic properties which differ between GaAs and SiGe devices, the two different materials also have different thermal conductivities which require somewhat different techniques for heat management.
The effective range of a wireless communication system depends on the maximum RF power that can be produced by that wireless communication system. The maximum RF power that can be produced by a device depends on the active device area, with the power capacity increasing as the active device area increases.
The bandwidth, or information transmission capacity, of a wireless communication system depends on the maximum frequency range that can be amplified effectively by that wireless communication system. As the power capacity and associated active device area of a device increases, the adverse effects of heat and increased parasitics also increase, so in practice it is generally the case that increasing the power capacity of a given device will decrease the maximum frequency range that can be amplified effectively by that device.
Especially for wireless communication systems, such as cell phones, that use batteries for electrical power, the so called power added efficiency (“PAE”) at which input battery power is converted to usable RF power (instead of being wasted, for example, as heat) determines how long such a device can be used before it must be recharged. For the reasons discussed above, device designs that maximize power added efficiency and RF power output while maintaining adequate high frequency performance are needed.
As discussed above, the power capacity of an active device increases as the active device area increases. For example, the maximum RF power level that can be produced by a BJT depends on the emitter area of the BJT, with the maximum RF power level increasing as the emitter area increases. Because of problems such as the emitter current crowding effect, it is known to divide the total emitter area of a BJT into multiple emitter “fingers” separated from one another. It is also known that the specific arrangement of these multiple emitter fingers can affect many aspects of the performance of such a device.
FIG. 1 shows an exemplary prior art BJT 20 having a base 22, emitter 24, collector 25, and multiple emitter fingers 26 separated by a uniform distance X 28. Although FIG. 1 is a compact layout that saves chip area, this type of layout is known to have poor thermal stability and performance due to severe thermal coupling between emitter fingers (they are too close) and excessive parasitic collector resistance.
FIG. 2 shows another exemplary prior art BJT 30 also having multiple emitter fingers 26. Unlike the device of FIG. 1, the multiple emitter fingers of the device of FIG. 2 are grouped into four subcells 32, with each of the four subcells 32 having two emitter fingers 26. In the device of FIG. 2, the subcells 32 are separated from one another by collector regions, with a uniform distance Y 34 between the centers of adjacent subcells 32. The device 30 of FIG. 2, although somewhat less compact than the device 20 of FIG. 1, is known to provide reduced collector resistance and thermal effects in exchange for the increased device area.
Although the device 20 of FIG. 1 and the device 30 of FIG. 2 have somewhat different performance characteristics, both devices have uniform spacing between the multiple emitter fingers 26 (in the device of FIG. 1) and between the multiple subcells 32 (in the device of FIG. 2). It is known that devices having uniformly spaced emitter fingers 26, or uniformly spaced emitter finger subcells 32, are typically subject to adverse thermal effects caused by a higher and localized device temperature rise in the center of these types of devices during operation, as further explained below.
When the transistors in the devices of FIGS. 1 and 2 are initially biased, equal current passes through each emitter finger 26, and this equal current produces an equal amount of heat in each finger. Over time, heat dissipates more slowly from the center fingers compared to the fingers on the periphery of the device. This is because the center fingers are surrounded by other emitter fingers that are also producing heat, unlike the peripheral fingers which are adjacent to cooler inactive regions where there are no emitter fingers producing heat. For this reason, devices like those of FIGS. 1 and 2 tend to operate with a non-uniform temperature distribution wherein the center fingers are hotter than the edge fingers.
It is also known that the non-uniform temperature distribution common to these types of devices can make them unstable at high output levels. The higher temperature of the center fingers can cause the so-called “current hogging” effect, wherein the higher temperature center fingers draw more current than the peripheral fingers subject to the same bias voltage. Current hogging occurs when the increased temperature of the center fingers causes an increase in current through those center fingers. The increased current through the center figures increases the heat produced in those center fingers, which in turn exacerbates the temperature difference between the hotter center fingers and the cooler peripheral fingers. Even if this effect does not cause the device to go completely unstable, it can nonetheless severely degrade device performance, for example by decreasing high frequency gain. In the worst case, thermal runaway and catastrophic failure occurs.
One prior art approach to improve the thermal stability and maintain a uniform junction temperature across the multiple emitter fingers 26, or multiple subcells 32, of a power transistor, is to connect equally- or unequally-valued ballast resistors 38 in series with each emitter finger 26 as shown in the device 36 of FIG. 3 and the device 40 of FIG. 4. These ballast resistors 38 typically have values in the range of 20-100 ohms, and provide a negative feedback mechanism between temperature and current of the emitter fingers or subcells. When more current is drawn by the center emitter finger 26 or subcell 32 due to the rising of temperature, the voltage drop across the ballast resistors 38 increases. Hence, the voltage available to the emitter fingers 26 is reduced and less heat is thus generated by these fingers.
Although ballast resistors 38 can provide thermal stability and improve temperature uniformity across the multiple emitter fingers 26, or emitter finger subcells 32, the use of ballast resistors 38 can adversely affect important measures of device performance. First, using ballast resistors will tend to reduce the maximum RF power output from the device. This is because the emitter fingers and subcells in series with the ballast resistors will be underbiased compared to a device without ballast resistors, since the available bias voltage must be shared between the ballast resistors and the remainder of the device. In addition, the ballasting resistors increase the RC delay and thereby adversely affect the high frequency performance of the device. Finally, the voltage drop across the ballast resistors ends up as heat instead of as RF output power, thereby wasting power and reducing the efficiency (“PAE”) of converting DC supply power into RF signal power for the power transistors.
Another prior art approach to improve the thermal stability and maintain a uniform junction across the multiple emitter fingers of a power transistor is to make the spacing between the emitter fingers non-uniform. This approach is discussed, for example, in U.S. Pat. No. 6,534,857. In this type of layout, the emitter finger spacing is non-uniform, with more spacing between the emitter fingers in the center region and less spacing between the edge fingers. The spacing is arranged with the goal of providing a uniform junction temperature across the emitter fingers. Similar benefits can be obtained by using progressively narrower widths of emitter fingers from the periphery toward the center region of the power transistor, or by using progressively shorter emitter finger lengths from the periphery toward the center region of the power transistor, for example as shown in U.S. Pat Nos. 5,616,950 and 5,850,099.
The aforementioned techniques involving non-uniform dimensioning and placement of the emitter fingers theoretically might produce thermal stability and uniform junction temperature regardless of the total number of emitter fingers in such a device. However, there are important practical limitations to this technique, especially for very large power transistors.
First, although it may be possible to calculate to a high degree of precision the dimensions and positions for emitter fingers that will optimize thermal stability and uniformity, it is much more difficult to actually manufacture emitter fingers in accordance with those calculated optimal dimensions and locations. The lithographic processes used to manufacture the emitter fingers always have statistical variations that cause the widths and locations of the emitter fingers to vary. This variation can be caused, for example, by variations in the optical column or mask used to print the emitter fingers, by variations in the photoresist or developer used to image the emitter fingers, or by variations in the etch or deposition processes used to prepare the emitter fingers. This variation can manifest itself, for example, in finger-to-finger variation within a transistor, in transistor-to-transistor variation within a batch, or in day-to-day variation between batches.
Second, although it may be possible to calculate to a high degree of precision the dimensions and positions for emitter fingers that will optimize thermal stability and uniformity, practical chip layout tools do not provide for arbitrarily small increments of dimensions and positions in design rules. Thus, especially when the dimensions and spacings of the emitter fingers are of the same order of magnitude as the minimum feature size available in the process being used to manufacture the transistors and/or the minimum dimension and location increments of the design rules of the software used to layout the transistor, there are important practical limits to realizing absolute uniformity of temperature and temperature stability using the prior art techniques involving non-uniform dimensioning and spacing of the emitter fingers.
Moreover, when the number of emitter fingers arranged in a single row becomes very large, the spacing non-uniformity of the emitter fingers residing in the center region of a power transistor becomes very gradual. As shown in FIG. 5, while emitter fingers 1 and 10 of a 10-finger power transistor fall on the outside edges of that 10-finger transistor, emitter fingers 1 and 10 of a 20-finger power transistor fall within the central area of that 20-finger transistor. Hence, more spacing will be required around emitter fingers 1 and 10 in the 20-finger transistor compared to the 10-finger transistor.
In comparison to the 10-finger power transistor where emitter fingers No. 4-7 are the center fingers, emitter fingers (No. 4-No. 16) in the 20-finger power transistor are all center fingers. The available space in the center area must be shared among all the center fingers, thus the central area of a 20 finger device becomes crowded because the edge area in a 20-finger device remains the same as in the 10-finger device. The difference in the theoretically optimum spacing between, for example, emitter fingers 4 and 5 and the spacing between emitter fingers 5 and 6 in a 20-finger device can be very small. The above-described practical limitations in manufacturing and design introduce variation in the dimensions and locations of emitter fingers that can result in significant temperature non-uniformity once the device's operation reaches its steady state.
Exacerbating the problem is the fact that the larger is the total number of emitter fingers in a power transistor, the higher is the junction temperature (FIG. 6). That is, without any statistical variations in emitter finger locations and dimensions, devices with a large number of emitter fingers run hotter than similarly constructed devices with fewer emitter fingers. Because devices with large numbers of emitter fingers run hotter, statistical variations in emitter fingers and locations can render these devices especially susceptible to current “hogging” due to the formation of local hot spots, or thermal runaway trigged by local non-uniformity of emitter finger width, e.g., statistical variation of the lithography feature size.
As a result, the dimensions and locations of the emitter fingers can be quite critical, and even small variations in dimensions can create large variations in temperature uniformity. FIG. 7(a) shows an exemplary prior art 23-emitter finger GaAs HBT, with nominal 2 μm finger width and nominal 20 μm finger length. The emitter fingers of the device of FIG. 7(a) are arranged in a non-uniform fashion to produce theoretically uniform junction temperatures, assuming that-the emitter fingers are manufactured to have perfect locations and dimensions.
FIGS. 7(b) and 7(c) present calculated steady-state temperature and current distributions of the device of FIG. 7(a) under the assumption that process variation has increased the width of the No. 12 emitter finger 42 to 2.02 μm. That is, the No. 12 emitter finger 42 is assumed to be 1% wider than the nominal 2 μ width of the other emitter fingers in the device of FIG. 7(a). FIG. 7(b) shows the calculated temperature profile across the emitter fingers resulting from this 1% variation in width of the no. 12 emitter finger 42. FIG. 7(c) shows the calculated current profile across the emitter fingers resulting from this 1% variation in width of the no. 12 emitter finger 42 during steady-state high power operation. These results show that even slight variations in finger dimensions can substantially degrade temperature uniformity and cause current hogging.
Generally, as the number of emitter fingers increases, smaller finger width variations will produce current hogging and temperature non-uniformity. Similarly, higher operating temperatures and higher output power tend to increase these adverse effects on temperature uniformity caused by process variation.
In summary, practical limitations in the manufacturing and design of power transistors having a very large number of emitter fingers limit the utility of non-uniform dimensioning and location of emitter fingers in achieving temperature uniformity and thermal stability in such devices. As a result, these prior art techniques are mainly useful for low and medium power transistors where not many emitter fingers are required. What is needed is a power transistor structure suitable for high power transistors using large numbers of emitter fingers and having better power performance, improved manufacturability, and more reliable thermal stability compared to prior-art power transistor structures. What is further needed are structures and dimensions which are particularly suited for SiGe applications, and other structures and dimensions which are particularly suited for GaAs applications.